Summer training Presentation

Presentation to be shown at 06/09/2013

ECE 5th semester!

Control engineering

Lecture plan

Digital system and circuits-II

Lecture plan

Organistaional behaviour- 5th sem

Lecture plan

Database management system

Lecture plan

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Communication system and circuit-II

Lecture plan

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Computer Architecture

Lecture plan ECE

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Software for Oracle

Software for oracle

Database management system

http://www.4shared.com/file/ND9w2o9L/Oracle_Database_10g_Express_Ed.html

Software for VHDL i.e Maxplus-II

Software downloading link

Maxplus-II 

VHDL

ftp://ftp.altera.com/outgoing/download/student102.exe

Dcs practical exprmnt-2 full subtractor behavorial

Full Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity fs is
port(a,b,bin:in bit;dif,bor:out bit);
end fs;

architecture behave of fs is
begin
process(a,b,bin)
begin
if(((a='0') and (b='0') and (bin='0')) or ((a='1') and (b='0') and
(bin='1')) or((a='1') and (b='1') and (bin='0'))) then
dif<='0';
bor<='0';
elsif(((a='0') and (b='0') and (bin='1')) or ((a='0') and (b='1') and
(bin='0')) or((a='1') and (b='1') and (bin='1'))) then
dif<='1';
bor<='1';
elsif((a='0') and (b='1') and (bin='1')) then
dif<='0';
bor<='1';
elsif((a='1') and (b='0') and (bin='0')) then
dif<='1';
bor<='0';
end if;
end process;
end behave;

D.C.S Lab-VHDL half subtractor

Half Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity hs is
port(a,b:in bit;dif,bor:out bit);
end hs;

architecture behaviour of hs is
begin
process(a,b)
begin
if(((a='0') and (b='0')) or((a='1') and (b='1'))) then
dif<='0';
bor<='0';
elsif(a='0') and (b='1') then
dif<='1';
bor<='1';
else
dif<='1';
bor<='0';
end if;
end process;
end behaviour;

CSC-II exprmnt-2 P.C.M. modulation AND demodulation

Pulse code Modulation and demodulation

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Control engineering MATLAB RAMP function

Matlab code for ramp function

clc;

clear all;

t=-50:1:50;
x=t;
plot(t,x);
axis([-50 50 -50 50]);
grid on;

Csc-II practical P.C.M. Modulation n Demodulation

Transmitter kit!

Reciever kit!

Demodulation ckt diagram

Dcs practical-II vhdl half adder behavioral

Half Adder Behavorial

library ieee;

use ieee.std_logic_1164.all;

entity ha2 is

port(a,b:in bit;s,c:out bit);

architecture bhv of ha2 is

begin

process (a,b)

begin

if a='o' and b='o'

then s<='0',c<='0';

elsif a='0' and b='1'

then s<='1', c<='0';

elsif a='1'and b='0'

then s<='1', c<='0';

else s<='1', c<='1';

end if;

end process;

end bhv;

Summer training,report submission

Guidelines for the report on summer training! As per notice board

Dbms practical-1 Creating table in oracle

Experiment-1

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Lecture Plan ECE 5th Sem all subjects,indraprastha university!

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Control Engineering- Introduction to MATLAB

Several operations on matrix