Communications system and circuits-II

Practical-7

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VHDL code for 4-bit Asynchronous binary Up-Counter

DCS-II Exp-7(a)

VHDL code for 4-bit binary Up-Counter

DBMS Practical Ex-3

Experiment-3

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Notice Board!

Exam might be preponed to saturday

Binary to Gray Using STRUCTURAL MODELLING

VHDL Code for Binary to Gray Using STRUCTURAL MODELLING

library ieee;

use ieee.std_logic_1164.all;

entity btog is

port(b3,b2,b1,b0: in bit; g3, g2, g1, g0: out bit);

Wavefrom and vhdl code for Binary to Gray converter

Wavefrom and vhdl code for Binary to Gray converter

Waveform for BINARY to GRAY and BINARY to EXCESS-3

VHDL code for Binary to GRAY

VHDL code for Binary to GRAY

DCS-II Experiment-5

library ieee;

use ieee.std_logic_1164.all;

entity b_to_g is 

port(b: in bit_vector(0 to 3); grey: out bit_vector( 0 to 3));

end b_to_g;

VHDL code for Binary to Excess-3

VHDL code for Binary to Excess-3 using DATAFLOW

DCS-II experiment-5

library ieee;

use ieee.std_logic_1164.all;

Attendance ECE-II

September 2013

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ADAPTIVE DELTA MODULATOR CSC-II Exp-4

ADAPTIVE DELTA MODULATOR

Communication system and circuits-II

Experiment-4

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Delta modulator CSC-II Exp-3

Delta modulator

Experiment-4

Communication system and circuits-II

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VHDL code For 4-Bit Parity Checker

4-Bit Parity Checker

library ieee;

use ieee.std_logic_1164.all;

entity pairity is

port(a:in bit_vector(0 to 3);o: out bit);

end pairity;

VHDL CODE for 2:4 ENCODER

2:4 ENCODER

library ieee;

use ieee.std_logic_1164.all;

entity encoder is

port(a: in bit_vector (0 to 3); o: out bit_vector(0 to 1));

end encoder;

architecture behave of encoder is

begin

process(a)

begin

if(a="1000")then

o<="00";

elsif(a="0100")then

o<="01";

elsif(a="0010")then

o<="10";

elsif(a="0001")then

o<="11";

end if;

end process;

Vhdl code for 16:1 MULTIPLEXER using structural modelling

16:1 MUX using 4:1 mux(structural modelling)

library ieee;

use ieee.std_logic_1164.all;

entity 16:1mux is

port(I:in bit_vector(0 to 15); S:in bit_vector(0 to 3); Y:out bit);

end 16:1mux;

architecture struct of 16:1mux is

signal Z0,Z1,Z2,Z3:bit;

component Multiplexr is

port(I0,I1,I2,I3,S0,S1:in bit;y:out bit);

end Multiplexr;

begin 

m1: multiplexr port map(I(0),I(1),I(2),I(3),S(0),S(1),Z0);

m2: multiplexr port map(I(4),I(5),I(6),I(7),S(0),S(1),Z1);

m3: multiplexr port map(I(8),I(9),I(10),I(11),S(0),S(1),Z2);

m4: multiplexr port map(I(12),I(13),I(14),I(15),S(0),S(1),Z3);

m5: multiplexr port map(Z0,Z1,Z2,Z3,S(2),S(3),Y);

end struct;

Vhdl code for 2:4 Decoder

2:4 Decoder using structural modelling!

library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port(a,b:in bit;d1,d2,d3,d4:out bit);

end decoder;

architecture decode of decoder is 

signal abar,bbar : bit;

Communication System - A. Bruce Carlson [Download]

Communication System

This is a Book to Learn Communication System. You can Either Purchase it on Google Books or I am Providing a Link to Download the PDF of this Book.

Computer Architecture tutorial

Tutorial sheets 1-3

Sheet-1

VHDL CODE FOR 1:4 DEMULTIPLEXER USING CASE STATEMENT DCS-II

EXPERIMENT-4(b)

vhdl code for 1:4 demux using case statement..

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a:in bit; s:in bit_vector(0 to 1);b,c,d,e:out bit);

VHDL Code for 4:1 multiplexer using case statement DCS-II

EXPERIMENT-4

VHDL code for 4:1 MUX

library ieee;

use ieee.std_logic_1164.all;

Communication system and circuits-II TUTORIAL- 3&4

Csc-II tut sheets 3 and 4

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Communication system and circuits-II TUTORIAL

Csc-II tutorial sheets tut-1 and 2

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List of experiments-Database management system

D.b.m.s

DATA BASE MANAGEMENT SYSTEM (ETCS-357)

Exercise 1 (Data Creation)

a)

The table given in the book by “Ivan Bayross”.

a)

Client_master(client no. , name , address1 , address2 , city , pincode , state , bal_due)

b)

Product_master (product_no.,description , profit percent , unit_measure, qty_on_hand, reorder_lvl ,sell_price,cost_price)

c)

Salesman_master (salesman_no.,salesman_name , address1 , address2 , city , pincode, state , sal_amt ,tgt_to_get,ytd_sales,remarks )

d)

Sales_order (order_no.,order_date,client_no.,dely_addr , salesman_no.,dely_type , billed_yn , dely_date, order_status)

e)

Sales_order_details(order_no.,product_no. ,qty_ordered , qty_disp ,product_rate )

D.B.M.S practical

Oracle. My sql plus

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VHDL code for 1:4 Demultiplexer (DEMUX)

VHDL Program for 1:4 DEMUX

library ieee;

use ieee.std_logic_1164.all;

entity demux is

port(a,s1,s0:in bit; b,c,d,e:out bit);

end demux;

architecture behave of demux is

begin

process(s1,s0)

4:1 Multiplexer(MUX) D.C.S-exprmnt-2 Waveform

VHDL code for 4:1 Multiplexer(MUX) D.C.S-exprmnt-2

VHDL Program For 4:1 Multiplexer 

library ieee;

use ieee.std_logic_1164.all;

entity mux is

port(a,b,c,d,s1,s0:in bit;o:out bit);

end mux;

architecture behaviour of mux is

begin

process(s1,s0)

begin

if(s1='0' and s0='0')then

o<=a;

elsif(s1='0' and s0='1')then

o<=b;

elsif(s1='1' and s0='0')then

o<=c;

else

o<=d;

end if;

end process;

end behaviour;

Summer training Presentation

Presentation to be shown at 06/09/2013

ECE 5th semester!

Control engineering

Lecture plan

Digital system and circuits-II

Lecture plan

Organistaional behaviour- 5th sem

Lecture plan

Database management system

Lecture plan

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Communication system and circuit-II

Lecture plan

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Computer Architecture

Lecture plan ECE

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Software for Oracle

Software for oracle

Database management system

http://www.4shared.com/file/ND9w2o9L/Oracle_Database_10g_Express_Ed.html

Software for VHDL i.e Maxplus-II

Software downloading link

Maxplus-II 

VHDL

ftp://ftp.altera.com/outgoing/download/student102.exe

Dcs practical exprmnt-2 full subtractor behavorial

Full Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity fs is
port(a,b,bin:in bit;dif,bor:out bit);
end fs;

architecture behave of fs is
begin
process(a,b,bin)
begin
if(((a='0') and (b='0') and (bin='0')) or ((a='1') and (b='0') and
(bin='1')) or((a='1') and (b='1') and (bin='0'))) then
dif<='0';
bor<='0';
elsif(((a='0') and (b='0') and (bin='1')) or ((a='0') and (b='1') and
(bin='0')) or((a='1') and (b='1') and (bin='1'))) then
dif<='1';
bor<='1';
elsif((a='0') and (b='1') and (bin='1')) then
dif<='0';
bor<='1';
elsif((a='1') and (b='0') and (bin='0')) then
dif<='1';
bor<='0';
end if;
end process;
end behave;

D.C.S Lab-VHDL half subtractor

Half Subtractor in VHDL behavorial

library ieee;
use ieee.std_logic_1164.all;

entity hs is
port(a,b:in bit;dif,bor:out bit);
end hs;

architecture behaviour of hs is
begin
process(a,b)
begin
if(((a='0') and (b='0')) or((a='1') and (b='1'))) then
dif<='0';
bor<='0';
elsif(a='0') and (b='1') then
dif<='1';
bor<='1';
else
dif<='1';
bor<='0';
end if;
end process;
end behaviour;

CSC-II exprmnt-2 P.C.M. modulation AND demodulation

Pulse code Modulation and demodulation

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Control engineering MATLAB RAMP function

Matlab code for ramp function

clc;

clear all;

t=-50:1:50;
x=t;
plot(t,x);
axis([-50 50 -50 50]);
grid on;

Csc-II practical P.C.M. Modulation n Demodulation

Transmitter kit!

Reciever kit!

Demodulation ckt diagram

Dcs practical-II vhdl half adder behavioral

Half Adder Behavorial

library ieee;

use ieee.std_logic_1164.all;

entity ha2 is

port(a,b:in bit;s,c:out bit);

architecture bhv of ha2 is

begin

process (a,b)

begin

if a='o' and b='o'

then s<='0',c<='0';

elsif a='0' and b='1'

then s<='1', c<='0';

elsif a='1'and b='0'

then s<='1', c<='0';

else s<='1', c<='1';

end if;

end process;

end bhv;

Summer training,report submission

Guidelines for the report on summer training! As per notice board

Dbms practical-1 Creating table in oracle

Experiment-1

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